technical data 394 8-bit bidirectional universal shift register with parallel i/o high-speed silicon-gate cmos the in74act299 is identical in pinout to the ls/als299, hc/hct299. the in74act299 may be used as a level converter for interfacing ttl or nmos outputs to high speed cmos inputs. the in74act299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. two mode-select inputs and two output enable inputs are used to choose the mode of operation as listed in the function table. synchronous parallel loading is accomplished by taking both mode- select lines, s 1 and s 2 , high. this places the outputs in the high- impedance state, which permits data applied to the data port to be clocked into the register. reading out of the register can be accomplished when the outputs are enabled. the active-low asynchronous reset overrides all other inputs. ? ttl/nmos compatible input levels ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 4.5 to 5.5 v ? low input current: 1.0 a; 0.1 a @ 25 c ? outputs source/sink 24 ma in74act299 ordering information IN74ACT299N plastic in74act299dw soic t a = -40 to 85 c for all packages pin assignment logic diagram pin 20=v cc pin 10 = gnd
in74act299 395 maximum ratings * symbol parameter value unit v cc dc supply voltage (referenced to gnd) -0.5 to +7.0 v v in dc input voltage (referenced to gnd) -0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) -0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, plastic dip+ soic package+ 750 500 mw tstg storage temperature -65 to +150 c t l lead temperature, 1 mm from case for 10 seconds (plastic dip or soic package) 260 c * maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recommended operating conditions. +derating - plastic dip: - 10 mw/ c from 65 to 125 c soic package: : - 7 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 4.5 5.5 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t j junction temperature (pdip) 140 c t a operating temperature, all package types -40 +85 c i oh output current - high -24 ma i ol output current - low 24 ma t r , t f input rise and fall time * (except schmitt inputs) v cc =4.5 v v cc =5.5 v 0 0 10 8.0 ns/v * v in from 0.8 v to 2.0 v this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
in74act299 396 dc electrical characteristics (voltages referenced to gnd) v cc guaranteed limits symbol parameter test conditions v 25 c-40 c to 85 c unit v ih minimum high-level input voltage v out = 0.1 v or v cc -0.1 v 4.5 5.5 2.0 2.0 2.0 2.0 v v il maximum low - level input voltage v out = 0.1 v or v cc -0.1 v 4.5 5.5 0.8 0.8 0.8 0.8 v v oh minimum high-level output voltage i out -50 a 4.5 5.5 4.4 5.4 4.4 5.4 v * v in =v ih or v il i oh =-24 ma i oh =-24 ma 4.5 5.5 3.86 4.86 3.76 4.76 v ol maximum low-level output voltage i out 50 a 4.5 5.5 0.1 0.1 0.1 0.1 v * v in = v ih or v il i ol =24 ma i ol =24 ma 4.5 5.5 0.36 0.36 0.44 0.44 i in maximum input leakage current v in =v cc or gnd 5.5 0.1 1.0 a ? i cct additional max. i cc /input v in =v cc - 2.1 v 5.5 1.5 ma i oz maximum three- state leakage current v in (oe)= v ih or v il v in =v cc or gnd v out =v cc or gnd 5.5 0.6 6.0 a i old +minimum dynamic output current v old =1.65 v max 5.5 75 ma i ohd +minimum dynamic output current v ohd =3.85 v min 5.5 -75 ma i cc maximum quiescent supply current (per package) v in =v cc or gnd 5.5 8.0 80 a * all outputs loaded; thresholds on input associated with output under test. +maximum test duration 2.0 ms, one output loaded at a time.
in74act299 397 ac electrical characteristics (v cc =5.0 v 10%, c l =50pf,input t r =t f =3.0 ns) guaranteed limits symbol parameter 25 c-40 c to 85 c unit min max min max f max maximum clock frequency (figure 1) 120 110 mhz t plh propagation delay, clock to q a ? or q h ? (figure 1) 4.0 12.5 3.0 14.0 ns t phl propagation delay, clock to q a ? or q h ? (figure 1) 4.0 13.5 3.5 15.0 ns t plh propagation delay, clock to q a thru q h (figure 1) 4.5 12.5 4.5 13.5 ns t phl propagation delay, clock to q a thru q h (figure 1) 5.0 15.0 4.5 16.5 ns t phl propagation delay, reset to q a ? or q h ? (figure 2) 4.0 15.0 4.0 18.0 ns t phl propagation delay, reset to q a thru q h (figure 2) 4.0 14.5 3.5 17.5 ns t pzh propagation delay , oe1, oe2 to q a thru q h (figure 3) 2.5 12.0 1.5 13.0 ns t pzl propagation delay , oe1, oe2 to q a thru q h (figure 3) 2.0 12.0 1.5 13.5 ns t phz propagation delay , oe1, oe2 to q a thru q h (figure 3) 2.0 12.5 2.0 13.5 ns t plz propagation delay , oe1, oe2 to q a thru q h (figure 3) 2.5 11.5 2.0 12.5 ns c in maximum input capacitance 4.5 4.5 pf typical @25 c,v cc =5.0 v c pd power dissipation capacitance 170 pf timing requirements (v cc =5.0 v 10%, c l =50pf, input t r =t f =3.0 ns) guaranteed limits symbol parameter 25 c-40 c to 85 c unit t su minimum setup time, mode select s1 or s2 to clock (figure 4) 5.0 5.5 ns t su minimum setup time, data inputs p a thru p h to clock (figure 4) 4.0 4.5 ns t su minimum setup time, data inputs s a , s h to clock (figure 4) 4.5 5.0 ns t h minimum hold time, clock to mode select s1 or s2 (figure 4) 1.0 1.0 ns t h minimum hold time, clock to data inputs p a thru p h (figure 4) 1.0 1.0 ns t h minimum hold time, clock to data inputs s a , s h (figure 4) 1.0 1.0 ns t rec minimum recovery time, reset inactive to clock (figure 2) 1.5 1.5 ns t w minimum pulse width, clock (figure 1) 4.0 4.5 ns t w minimum pulse width, reset (figure 2) 3.5 3.5 ns
in74act299 398 function table inputs response mode reset mode select output enables clock serial inputs p a / q a p b / q b p c / q c p d / q d p e / q e p f / q f p g / q g p h / q h q a ?q h ? s 2 s 1 oe1 oe2 d a d h reset l x l l l x x xlllllll l l l l l x l l x x xlllllll l l l lhhx x x xx q a through q h =z l l shift right h l h h x d x shift right: q a through q h =z; d a f a ; f a f b ; etc dq g h l h x h d x shift right: q a through q h =z; d a f a ; f a f b ; etc dq g h l h l l d x shift right: d a f a =q a ; f a f b =q b ; etc dq g shift left h h l h x x d shift left: q a through q h =z; d h f h ; f h f g ; etc q b d h h l x h x d shift left: q a through q h =z; d h f h ; f h f g ; etc q b d h h l l l x d shift left: d h f h =q h ; f h f g =q g ; etc q b d parallel load h h h x x x x parallel load:p n f n p a p h hold h l l h x x x x hold: q a through q h =z; f n =f n p a p h h l l x h x x x hold: q a through q h =z; f n =f n p a p h h l l l l x x x hold: q n =q h p a p h z = high impedance d = data on serial input f = flip-flop (see logic diagram) when one or both output controls are high the eight input/output terminals are disabled to the high- impedance state; however, sequential operation or clearing of the register is not affected.
in74act299 399 figure 1. switching waveform figure 2. switching waveform figure 3. switching waveform figure 4. switching waveform
in74act299 400 expanded logic diagram
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